Regviz

Microchip Technology /ATSAMV71N20 /PWM0 /LEBR1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LEBR1

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAMV71J20/PWM0/LEBR1#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LEBDELAY0 (PWMLFEN)PWMLFEN 0 (PWMLREN)PWMLREN 0 (PWMHFEN)PWMHFEN 0 (PWMHREN)PWMHREN

Description

PWM Leading-Edge Blanking Register (trg_num = 1)

Fields

LEBDELAY

Leading-Edge Blanking Delay for TRGINx
PWMLFEN

PWML Falling Edge Enable
PWMLREN

PWML Rising Edge Enable
PWMHFEN

PWMH Falling Edge Enable
PWMHREN

PWMH Rising Edge Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data